1. Field of the Invention
This invention generally relates to an amplification circuit, and particularly relates to an amplification circuit with improved linearity. This invention has particular applicability to an amplification circuit which includes a differential amplifier.
2. Description of the Background Art
Generally, in an amplification circuit, linearity is required between an input signal and an output signal through a wide range of input signal levels. For example, a receiving circuit for use in a cordless telephone, a transceiver or a similar device is provided with an amplification circuit for amplifying received voice signals.
Generally, some noise other than a voice signal is included in a received radiowave. This means that when the level of the voice signal is low, the noise becomes relatively more prominent compared to the voice signal. It is therefore necessary to amplify the voice signal by the amplification circuit. In particular, as the voice signal changes over a wide range of signal level, the amplification circuit is required to have a wide dynamic range, i.e. linearity between the input and output.
A differential amplifier is frequently used in an amplification circuit for various electrical signals, including the amplification circuit for the above mentioned voice signal. However, since a differential amplifier typically has non-linearity between the input signal and the output signal, it can often introduce distortion into the amplified voice signal.
FIG. 1 is a circuit diagram of a conventional amplification circuit utilizing a differential amplifier as discussed above. The amplification circuit includes a first differential amplifier having of npn transistors 1 and 2, constant current sources 3 and 4, and resistor 5; a second differential amplifier having diodes 6 and 7 for converting an output signal generated from the differential amplifier into a logarithmic signal, npn transistors 8 and 9 and a variable current source 10, and a current mirror circuit composed of pnp transistors 11 and 12. The second differential amplifier and the current mirror circuit form an exponential conversion circuit for exponent- converting a logarithm converted signal.
Transistor 1 has its base connected to receive an input signal V. Transistor 2 has its base connected to receive a predetermined constant voltage V.sub.B. Transistor 1 is grounded through a constant voltage source 3 with an emitter capable of passing a constant current I.sub.D. Transistor 2 is grounded through a constant current source 4 with an emitter capable of passing a constant current I.sub.D. Resistor 5 is connected between the emitters of the transistors 1 and 2. Resistor 5 is provided to increase the gain of the first differential amplifier.
Diodes 6 and 7 are connected between a power supply V.sub.cc and the collectors of transistors 1 and 2 respectively. Transistor 8 has its base connected to collector of the transistor 2. Transistor 9 has its base connected to the collector of transistor 1. The emitters of transistors 8 and 9 are connected together, and connected between the common connection node and ground is a variable current source 10 capable of passing a variable current I.sub.G. Transistor 11 is connected between the power supply V.sub.cc and the collector of the transistor 8, and also connected to diode 6 and 7. Transistor 12 is connected between the power supply V.sub.cc and transistor 9. An output current Io is generated through the common connection node of transistors 9 and 12.
In operation, input signal V is applied to the base of transistor 1, and then the applied input signal V is converted into a current signal by transistors 1 and 2. This converted current signal is converted into a logarithmic signal by diodes 6 and 7 and the, the two logarithm-converted signals are applied to the bases of transistors 8 and 9. The output current I.sub.O is determined, based on the product of the voltage between the bases of the transistors 8 and 9 and the variable current I.sub.G is thus output through the collector of transistor 9.
This operation of the amplification circuit shown in FIG. 1 gives rise to the following problems related to its linearity. Resistor 5 is connected between the emitters of transistors 1 and 2, the non-linear internal resistance of the emitters of transistors 1 and 2 cannot be ignored, when input signal V is converted into a current signal. More specifically, when the emitter current of the transistor 1 is I.sub.E, the emitter resistance of the transistors 1 and 2 is r.sub.E, and the resistance value of the resistor 5 is R, I.sub.E is represented by the following equation. EQU I.sub.E =(V-V.sub.B)/(R+2.multidot.r.sub.e) (1)
In order to improve the linearity of the current conversion conducted by the transistors 1 and 2, it is necessary to reduce the effect of the internal resistance of the emitter r.sub.e on the emitter current I.sub.E. It is necessary to reduce the internal resistance of the emitter r.sub.e by either making the value R of the resistance 5 represented by R&gt;&gt;2.multidot.r.sub.e, or increasing the emitter current I.sub.E. However, the former approach decreases the gain of the amplification circuit. On the other hand, the latter approach causes increased current consumption. As a result, it is not possible to improve the linearity as well as to secure the wide dynamic range, without causing a decrease of the gain of the circuit or increasing the current consumption.
FIG. 2 is a circuit diagram of a conventional multiplying circuit utilizing the differential amplifier indicated in FIG. 1. Referring to FIG. 2, this multiplying circuit comprises a first differential amplifier having npn transistors 103, 104, 106 and 107, and a resistor 108; a current mirror circuit with pnp transistors 109 and 110; a current mirror circuit with pnp transistors 111 and 112; a multiplier having pnp transistors 121, 122, 123 and 124; and a second differential amplifier with pnp transistors 16 and 117 and resistor 118. This multiplication circuit receives the input signals V.sub.L and V.sub.R to generate an output current I.sub.OUT determined by multiplication of V.sub.L and V.sub.R.
In operation, as the input signal V.sub.L is applied to the base of transistor 106, the input signal V.sub.L is converted into a current signal by transistors 106, 107, and resistor 108. The collector current of transistor 106 is applied to the emitters of transistors 121 and 122 through the transistors 109 and 110. The collector current of transistor 107 is applied to the emitters of transistors 123 and 124 through transistors 111 and 112.
As the input signal V.sub.R is applied to the base of the transistor 116, the signal is converted into a current signal by transistors 116, 117, and resistor 118. The individual collector currents of transistors 116 and 117 are converted into logarithmic signals by diodes 119 and 120 respectively. The two converted signals are applied to the bases of transistors 122 and 123, and the bases of transistors 121 and 124 respectively. As a result, multiplication of V.sub.L and V.sub.R is carried out by transistors 121, 122, 123 and 124 whereby current I.sub.OUT is obtained.
The multiplication circuit indicated in FIG. 2 also creates a similar problem to that which occurs in the amplification circuit indicated in FIG. 1. In the multiplication circuit indicated in FIG. 2, the resistor 108 is connected between the emitters of transistors 106 and 107 which form the first differential amplifier. The non-linear emitter resistance of transistors 106 and 107 included therein therefore cannot be ignored, when the input signal V.sub.L is converted into a current signal. Likewise, as the resistance 118 is connected between the emitters of transistors 116 and 117, in current conversion of the input signal V.sub.R, the non-linear emitter resistance of transistors 116 and 117 cannot be ignored.
More practically, when the emitter current of transistors 106 and 116 are I.sub.E1 and I.sub.E2 respectively, the internal resistance each of the emitters of transistors 106, 107, 116 and 117 is r.sub.e, and each resistance value of resistors 108 and 118 are R1 and R2 respectively, I.sub.E1, I.sub.E2 and I.sub.OUT will be represented by the following equations. EQU I.sub.E1 =(V.sub.L -V.sub.B)/(R1+2.multidot.r.sub.e) (2) EQU I.sub.E2 =(V.sub.R -V.sub.B)/(R2+2.multidot.r.sub.e) (3) EQU I.sub.OUT =2.multidot.I.sub.E1 .multidot.I.sub.E2 /I.sub.D ( 4)
When equations (2) and (3) are substituted in equation (4), the following equation can be obtained. ##EQU1##
As is the case with the amplification circuit indicated in FIG. 1, it is preferable for the value 2.multidot.r.sub.e to be negligible, in order to secure good linearity of the multiplication circuit indicated in FIG. 2.
It is necessary therefore for each internal resistance of the emitter r.sub.e of the transistors 106, 107, 116 and 117 to be reduced by making the relation of the values represented by R1&gt;&gt;2.multidot.r.sub.e and R2&gt;&gt;2.multidot.r.sub.e or by increasing the emitter currents I.sub.E1 and I.sub.E2. However, in the former case, decrease in the gain of the multiplication circuit indicated in FIG. 2 cannot be avoided. In the latter case, however an undesirable increase in current consumption is unavoidable.